Designers are constantly striving to improve programmable data processors such as microprocessors and digital signal processors. A problem faced by designers of programmable data processors is known as code bloat. With instruction lengths generally set at 32 bits, the amount of memory required to store instructions may be very large. It is known that many commonly used instructions could be coded with fewer bits, such as 16 bits because these instructions do not need to specify three data registers or because all possible signaling and control functions are not relevant and need not be coded. In many useful product applications at least a significant portion of the system program could be specified with instruction words shorter than the standard length. The designer is left with the problem of distinguishing between this shorter instruction word code and the normal length instruction word code.
A known solution to this problem involves data processor modes. The data processor has a normal mode which operates in the same manner as the prior data processor in the same family. An alternative mode enables access to alternate or extended instructions including smaller length instructions not present in the original instruction set. Generally such data processor modes are invoked by a mode instruction in each mode. A normal mode instruction when executed switches the data processor to the alternative mode. An alternative mode instruction when executed switches the data processor to the normal mode.
Such data processor modes achieve their purpose of enabling the alternative short length instructions but introduce additional problems. Tracking the current data processor mode and insuring that the instructions to be executed are appropriate for the current mode is a problem. Often there is a significant overhead in changing modes. This prevents free mixing of normal mode and extended mode instructions. When implementing a smaller length instruction set, only commonly used instructions are encoded because of limited opcode space. Thus data processor modes are not a completely satisfactory solution to this problem.
The mixing of different instruction sizes presents several problems. Use of shorter instructions promises to reduce the code size of software. Such mixing introduces complexities in code generation by selecting instruction sizes early in the code generation phase. These complexities include honoring architectural constraints while trying to schedule instructions and honoring architectural constraints while attempting to perform any optimization or necessary transformation during the code generation phase of a compiler.